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GR533X_不添加DTM工程直接输出单载波方法分享 GR533x

181***366

2023-12-25 11:01

在整机测试工位需要测试频偏,因整机已装好外壳无法使用串口,通常使用蓝牙发命令直接让固件输出单载波,方法分享如下:

1. 如果有开广播或者进行连接,需要先调ble_gap_adv_stop或ble_gap_disconnect将BLE业务停掉,并且需要在这两个的回调中断之后再调用如下send_signal_carrier_wave_ext单载波函数;

2. GR533X内部有3个PA,当前具体使用哪一个PA可以搜索RF_TX_PA_SELECT宏定义;

3. 单载波测试完后需要调用芯片复位接口或者是重新上电对芯片进行复位;

4. channel传参对应物理通道0-39,发射功率可根据备注进行配置;

实现示例代码如下:

#define REG_32BIT_WR(addr, value) (*(volatile uint32_t *)(addr)) = (value)

#if RF_TX_PA_SELECT == 1 //BLE_RF_TX_MODE_SPA_MODE -20~6
void send_signal_carrier_wave_ext(uint8_t channel)
{
    if (channel > 39)
        return;

    REG_32BIT_WR(0x4000a4e0,0x00000003);
    REG_32BIT_WR(0x4000a4e0,0x00000001);
    REG_32BIT_WR(0x4000a4e0,0x00000005);
    REG_32BIT_WR(0x4000a4c0,0x00000001);
    REG_32BIT_WR(0x4000a4c0,0x00000002);
    REG_32BIT_WR(0x400f5000,0x00000008);
    REG_32BIT_WR(0x400f5018,0x000001F0);
    REG_32BIT_WR(0x400f501c,(2402 + channel * 2) * 0x10000);
    REG_32BIT_WR(0x400f2064,0x4104019A);
    REG_32BIT_WR(0x400f2080,0x88101940);
    REG_32BIT_WR(0x400f2084,0x4F88100F);
    REG_32BIT_WR(0x400f2058,0X90C8407A);
    //reset and enable SXPLL, PA
    REG_32BIT_WR(0x400F1020,0x80000000);
    REG_32BIT_WR(0x400f202C,0x11002000);
    REG_32BIT_WR(0x400f202C,0x35000000);
    // { 0x02 }, // -20
    // { 0x03 }, // -15
    // { 0x05 }, // -10
    // { 0x07 }, // -8
    // { 0x0b }, // -5
    // { 0x10 }, // 0
    // { 0x12 }, // 1
    // { 0x18 }, // 2
    // { 0x23 }, // 3
    // { 0x2F }, // 4
    // { 0x3F }, // 5
    //5dbm 0x00003f10 //0dbm 0x00001010
    REG_32BIT_WR(0x400f3040,0x00003F10); //bit8-bit15
}
#endif

#if RF_TX_PA_SELECT == 2 //BLE_RF_TX_MODE_UPA_MODE -15~2
void send_signal_carrier_wave_ext(uint8_t channel)
{
    if (channel > 39)
        return;

    REG_32BIT_WR(0x4000a4e0,0x00000003);
    REG_32BIT_WR(0x4000a4e0,0x00000001);
    REG_32BIT_WR(0x4000a4e0,0x00000005);
    REG_32BIT_WR(0x4000a4c0,0x00000001);
    REG_32BIT_WR(0x4000a4c0,0x00000005);
    REG_32BIT_WR(0x400f5000,0x00000008);
    REG_32BIT_WR(0x400f5018,0x000001F0);
    REG_32BIT_WR(0x400f501c,(2402 + channel * 2) * 0x10000);
    REG_32BIT_WR(0x400f2064,0x4104019A);
    REG_32BIT_WR(0x400f2080,0x88101040);
    REG_32BIT_WR(0x400f2084,0x3F88108F);
    REG_32BIT_WR(0x400F205C,0X00000080);
    REG_32BIT_WR(0x400f2058,0X90C8407A);
    //reset and enable UXPLL, PA
    REG_32BIT_WR(0x400F1020,0x80000000);
    REG_32BIT_WR(0x400f202C,0x11002000);
    REG_32BIT_WR(0x400f202C,0x35000000);
    // {0x01 }, // -18
    // {0x02 }, // -12
    // {0x03 }, // -10
    // {0x04 }, // -8
    // {0x06 }, // -5
    // {0x08 }, // -3
    // {0x09 }, // -2
    // {0x0B }, // -1
    // {0x0F }, // 0
    //0dbm 0x00000f10 -10dbm 0x00000310
    REG_32BIT_WR(0x400f3040,0x00000f10); //bit8-bit15
}
#endif

#if RF_TX_PA_SELECT == 3 //BLE_RF_TX_MODE_HPA_MODE -10~15
void send_signal_carrier_wave_ext(uint8_t channel)
{
    if (channel > 39)
        return;

    REG_32BIT_WR(0x4000a4e0,0x00000003);
    REG_32BIT_WR(0x4000a4e0,0x00000001);
    REG_32BIT_WR(0x4000a4e0,0x00000005);
    REG_32BIT_WR(0x4000a4c0,0x00000001);
    REG_32BIT_WR(0x4000a4c0,0x00000005);
    REG_32BIT_WR(0x400f5000,0x00000008);
    REG_32BIT_WR(0x400f5018,0x000001F0);
    REG_32BIT_WR(0x400f501c,(2402 + channel * 2) * 0x10000);
    REG_32BIT_WR(0x400f2064,0x410401D8);
    REG_32BIT_WR(0x400f2080,0x88101040);
    REG_32BIT_WR(0x400f2084,0x3F88108F);
    REG_32BIT_WR(0x400F2034,0x00000201);
    REG_32BIT_WR(0x400F2130,0XFF);
    REG_32BIT_WR(0x400F2054,0xDE533985);
    REG_32BIT_WR(0x400f2058,0X28553985);
    //reset and enable HXPLL, PA
    REG_32BIT_WR(0x400F1020,0x80000000);
    REG_32BIT_WR(0x400f202C,0x11002000);
    REG_32BIT_WR(0x400f202C,0x35000000);
    // {0x81 }, // -10
    // {0x83 }, // -8
    // {0x84 }, // -3
    // {0x86 }, // 1
    // {0x88 }, // 4
    // {0x8A }, // 6
    // {0x8C }, // 7
    // {0x8E }, // 8
    // {0x90 }, // 9
    // {0x92 }, // 10
    // {0x96 }, // 11
    // {0x9A }, // 12
    // {0xA0 }, // 13
    // {0xA8 }, // 14
    // {0xBF }, // 15
    //15dbm 0x0000bf10 1dbm 0x00008610
    REG_32BIT_WR(0x400f3040,0x00008610); //bit8-bit15
}
#endif


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181***366

2023-12-25 11:24

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